The term “MOS” has been used for a metal-oxide-semiconductor layered structure from long ago. Particularly in field effect transistors of MOS structure (hereinafter briefly referred to as “MOS transistors”), however, materials for a gate insulating film and gate electrode are being improved with the recent trend toward higher integration and improved manufacturing process.
For instance, polycrystalline silicon is employed as a gate electrode material instead of metal in MOS transistors, mainly in terms of forming a source/drain in a self-aligned manner. From the view point of achieving improved electric properties, materials of high dielectric constant are employed, which are not necessarily limited to oxides.
Accordingly, the term “MOS” is not limited to the metal-oxide-semiconductor layered structure, and the description throughout the present specification is not based on such limitation. That is, in light of common technical knowledge, the term “MOS” herein is not a mere abbreviation of metal-oxide-semiconductor, but widely involves conductor-insulator-semiconductor layered structures.
FIG. 84 is a plan view showing a first mode of layout of a conventional MOS transistor formed in a SOI layer in a SOI substrate including a support substrate, a buried insulating film and the SOI layer.
In FIG. 84, a gate electrode 93 is formed on a body region (with a channel region on its surface; both not shown) between a source region 91 and a drain region 92 with a gate oxide film (not shown) interposed therebetween. A full isolation region 100 extending through the SOI layer is provided around these transistor forming regions 91 to 93.
FIG. 85 is a plan view showing a second mode of layout of a conventional MOS transistor formed in a SOI layer in a SOI substrate.
In FIG. 85, similarly to the first mode, the gate electrode 93 is formed on a body region between the source region 91 and drain region 92 with a gate oxide film interposed therebetween, and the full isolation region 100 is provided around these transistor forming regions 91 to 93.
Further, in the second mode, a source tie region 94 extends from part of an upper portion of the region where the source region 91 is provided to part of an upper portion of the region where the body region is provided. Since the source tie region 94 is adjacent to both the source region 91 and body region, its potential is set through metal silicide for setting the potential of the source region 91, by which potential setting of the body region is achieved.
Techniques for fixing the body region potential of such MOS transistor formed on a SOI substrate include a SOI semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 2002-289873, for example.
The body potential fixing using the source tie region 94 of the aforementioned second mode and body potential fixing disclosed in the above JP2002-289873 arise problems of not ensuring higher integration, lower parasitic capacitance and smaller wiring capacitance as well as achieving stable body potential fixing.